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[AKD4673-A]
AKD4673-A
Evaluation board Rev.0 for AK4673
GENERAL DESCRIPTION AKD4673 is an evaluation board for the AK4673, stereo CODEC with built-in MIC/HP amplifier and TSC. The AKD4673 can evaluate A/D converter and D/A converter of the CODEC separately in addition to loopback mode (A/D D/A). The AKD4673 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Moreover, the AKD4673 can also evaluate A/D converter of the TSC with the control software. Ordering guide
AKD4673 --Evaluation board for AK4673 (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * RCA connector for an external clock input * 10pin Header for serial control mode * Touch-Panel I/F
DVDD TVDD AVDD HVDD Opt In Opt Out GND REG
3.3V
REG
LIN1/RIN1 AK4114 LIN2/3/4 RIN2/3/4 MIN Digital Audio I/F 10Pin Header
AK4673
LOUT ROUT HP Jack HPL HPR
Control I/F 10Pin Header
Figure 1. AKD4673 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual
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Operation sequence
(1) Set up the power supply lines. (1-1) In case of using the regulator. Set up the jumper pins. JP3 JP4 JP5 HVDD_SEL AVDD_SEL DVDD_SEL Short Short Short JP6 TVDD_SEL Short JP7 VCC_SEL Short JP106 TVDD2 Short JP107 TVDD1 Short JP109 TSVDD Short
JP State
Set up the power supply lines. [REG] (red) = 5.0V [D3V] (orange) [AGND] (black) [DGND] (black)
: for regulator (3.3V output : HVDD, AVDD, TVDD1, TVDD2, TSVDD, DVDD of AK4673) = 2.7 3.6V : for AK4114 and logic (typ. 3.3V) = 0V : for analog ground = 0V : for logic ground
(1-2) In case of using the power supply connectors. Set up the jumper pins. JP3 JP4 JP5 HVDD_SEL AVDD_SEL DVDD_SEL Open Open Open JP6 TVDD_SEL Open JP7 VCC_SEL Open JP106 TVDD2 Short JP107 TVDD1 Short JP109 TSVDD Short
JP State
Set up the power supply lines. [HVDD] (orange) = 1.6 ~ 3.6V [AVDD] (orange) = 1.6 ~ 3.6V [DVDD] (orange) = 1.6 ~ 3.6V [TVDD] (orange) = 1.6 ~ 3.6V [VCC] (orange) = 1.6 3.6V [D3V] (orange) = 2.7 3.6V [AGND] (black) = 0V [DGND] (black) = 0V
: for HVDD of AK4673 (typ. 3.3V) : for AVDD and PVDD of AK4673 (typ. 3.3V) : for DVDD of AK4673 (typ. 3.3V) : for TVDD1, TVDD2, TSVDD of AK4673 (typ. 3.3V) : for logic (typ. 3.3V: = DVDD) : for AK4114 and logic (typ. 3.3V) : for analog ground : for logic ground
* Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) (3) Power on. The AK4673 and AK4114 should be resets once bringing SW1 (PDN) and SW2 (DIR) "L" upon power-up.
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Evaluation mode
In case of AK4673 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4673 and AK4114. About AK4673's audio interface format, refer to datasheet of AK4673. About AK4114's audio interface format, refer to Table 2 in this manual. Evaluation of CODEC (1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4114 (1-2) Evaluation of D/A using DIR of AK4114 (1-3) Evaluation of Loop-back using AK4114 (1-4) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4114 (2-2) Evaluation of D/A using DIR of AK4114 (2-3) Evaluation of Loop-back using AK4114 (2-4) Evaluation of Loop-back that master clock is fed externally (3) PLL Slave Mode (3-1) PLL Reference Clock : MCKI pin (3-1-1) Evaluation of A/D, D/A using PORT3 (DSP) (3-1-2) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board (3-2) PLL Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4114 (3-2-2) Evaluation of D/A using DIR of AK4114 (3-2-3) Evaluation of Loop-back using AK4114 (4) PLL Master Mode (4-1) Evaluation of Loop-back using AK4114 (4-2) Evaluation of Loop-back that master clock is fed externally (4-3) Evaluation of Internal Loop-back using clock is fed externally
Evaluation of TSC (1) Position, Pen Pressure
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Evaluation of CODEC JP104, JP102 should be set to short. JP103, JP105 should be set to open. (1) External Slave Mode When PMPLL bit is "0", the AK4673 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits. JP23 (M/S) should be set to "Slave". In addition, the register of AK4673 should be set to "EXT Slave Mode".
AK4673
MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDTO SDTI 32fs 1fs MCLK BCLK LRCK SDTI SDTO
DSP or P
Figure 2. EXT Slave Mode (1-1) Evaluation of A/D using DIT of AK4114 PORT2 (DIT) and X1 (X'tal) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set to the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP19 PHASE THR INV
JP22 4114_MCKI
(1-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set to the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
When AK4114 is used, JP16 (MKFS) and JP17 (BCFS) are not used. Therefore, JP16 (MKFS) should be set to "256fs" and JP23 (BCFS) should be set to "64fs". * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can't be used.
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(1-3) Evaluation of Loop-back using AK4114 X1 (X'tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set to the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
JP22 4114_MCKI
When AK4114 is used, JP16 (MKFS) and JP17 (BCFS) are not used. Therefore, JP16 (MKFS) should be set to "256fs" and JP23 (BCFS) should be set to "64fs". * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can't be used.
(1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by on-board divider. J11 (EXT) is used. MCKI is supplied from J11 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-A. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
When a termination (51) is unnecessary, please set JP14 (EXT) open. JP16 (MKFS), JP17 (BCFS), and JP20 (LRCK) should be set according to the frequency of MCLK, BICK and LRCK.
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(2) External Master Mode The AK4673 becomes EXT Master Mode by setting PMPLL bit = "0" and M/S bit = "1". Master clock can be input via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 512fs, or 1024 fs). The input frequency of MCKI is selected by FS1-0 bits. JP23 (M/S) should be set to "Master". In addition, the register of AK4673 should be set to "EXT Master Mode".
AK4673
MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDTO SDTI 32fs or 64fs 1fs MCLK BCLK LRCK SDTI SDTO
DSP or P
Figure 3. EXT Master Mode
(2-1) Evaluation of A/D using DIT of AK4114 X1 (X'tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 13. BCKO bit = "1" (Register Address 04H) The jumper pins should be set as the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP19 PHASE THR INV
JP22 4114_MCKI
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can't be used.
(2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 13. BCKO bit = "1" (Register Address 04H). The jumper pins should be set as the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can't be used.
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(2-3) Evaluation of Loop-back using AK4114 X1 (X'tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
JP22 4114_MCKI
JP16 (MKFS) should be set according to the frequency of MCLK.
(2-4) Evaluation of Loop-back where master clock is fed externally J11 (EXT) is used. MCKI is supplied from J11 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-A. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
*When a termination (51) is unnecessary, please set JP14 (EXT) open. JP16 (MKFS) should be set according to the frequency of MCLK.
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(3) PLL Slave Mode A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4673 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits. JP23 (M/S) should be set to "Slave". In addition, the register of AK4673 should be set to "PLL Slave Mode". (3-1) PLL Reference Clock : MCKI pin
11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK4673
MCKI MCKO BICK LRCK SDTO SDTI
DSP or P
256fs/128fs/64fs/32fs 32fs 1fs
MCLK BCLK LRCK SDTI SDTO
Figure 4. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) (3-1-1) Evaluation of A/D, D/A using PORT3 (DSP) PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and J11 (EXT). SDTI, SDTO, LRCK and BICK of PORT3 are respectively connected with SDTO, SDTI, LRCK and BICK of DSP. Connect the test pin (MCKO) to DSP when MCKO is supplied to DSP. The jumper pins should be set as the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
(3-1-2) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board J11 (EXT) is used. MCKI is supplied from J11 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-A.Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
*When a termination (51) is unnecessary, please set JP14 (EXT) open. JP16 (MKFS) should be set to MCKO; JP17 (BCFS), and JP20 (LRCK) should be set according to the frequency of BICK and LRCK. -82007/5
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(3-2) PLL Reference Clock : BICK or LRCK pin
AK4673
MCKO MCKI BICK LRCK SDTO SDTI 32fs or 64fs 1fs BCLK LRCK SDTI SDTO
DSP or P
Figure 5. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4673
MCKO MCKI BICK LRCK SDTO SDTI 32fs 1fs BCLK LRCK SDTI SDTO
DSP or P
Figure 6. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
(3-2-1) Evaluation of A/D using DIT of AK4114 X1 (X'tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR), PORT3 (DSP) and J11 (EXT). The jumper pins should be set as the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL
JP21 JP22 LRCK_SEL 4114_MCKI
JP19 PHASE
DIR
4040
DIR
4040
THR
INV
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can't be used.
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(3-2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT), PORT3 (DSP) and J11 (EXT). The jumper pins should be set as the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL
JP21 LRCK_SEL
JP19 PHASE
JP24 SDTI_SEL
DIR
4040
DIR
4040
THR
INV
DIR
ADC
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can't be used.
(3-2-3) Evaluation of Loop-back using AK4114 X1 (X'tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT), PORT3 (DSP) and J11 (EXT). The jumper pins should be set as the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL
JP22 JP21 LRCK_SEL 4114_MCKI
JP19 PHASE
JP24 SDTI_SEL
DIR
4040
DIR
4040
THR
INV
DIR
ADC
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can't be used.
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(4) PLL Master Mode When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit. JP23 (M/S) should be set to "Master". In addition, the register of AK4673 should be set to "PLL Master Mode".
11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK4673
MCKI MCKO BICK LRCK SDTO SDTI
DSP or P
256fs/128fs/64fs/32fs 32fs, 64fs 1fs
MCLK BCLK LRCK SDTI SDTO
Figure 7. PLL Master Mode (4-1) Evaluation of Loop-back using AK4114 X1 (X'tal) is used. Nothing should be connected to PORT1 (DIR), PORT3 (DSP) and J11 (EXT). Using the AK4673's internal PLL it is possible to evaluate various sampling frequencies. The jumper pins should be set to the following.
JP15 MCLK DIR EXT
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
(4-2) Evaluation of Loop-back that master clock is fed externally J11 (EXT) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). Exclude X'tal oscillator from X1. Using the AK4673's internal PLL it is possible to evaluate various sampling frequencies. The jumper pins should be set to the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
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(4-3) Evaluation of Internal Loop-back using clock is fed externally J11 (EXT) is used. Nothing should be connected to PORT1(DIR) and PORT3 (DSP). It can be evaluated at internal loop-back mode (LOOP bit = "1"). Using the AK4673's internal PLL it is possible to evaluate various sampling frequencies. The jumper pins should be set to the following.
JP14 EXT DIR EXT
JP15 MCLK
JP18 BICK_SEL DIR 4040
JP21 LRCK_SEL DIR 4040
JP24 SDTI_SEL DIR ADC
JP19 PHASE THR INV
Evaluation of TSC PORT4 (CTRL) should be directly connected to the parallel port. (Figure 9) JP103, JP105 should be set to short. JP102, JP104 should be set to open. (1) Position, Pen Pressure 4-wire touch-panel (X+, X-, Y+ and Y-) should be connected to J100 connector as the following figure.
Figure 8. Connect of Touch Panel
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DIP Switch set up
[S1] : Mode Setting of AK4114 and AK4673 ON is "H", OFF is "L". No. 1 2 3 4 5 6 Name DIF2 DIF1 DIF0 OCKS1 CAD0 I2C ON ("H") OFF ("L") Default ON OFF OFF OFF OFF OFF
AK4114 Audio Format Setting See Table 2 AK4114 Master Clock Setting : See Table 3 AK4673Control Mode Setting : See Table 4 Table 1. Mode Setting for AK4673 and AK4114 LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I
DIF2 0 0 0 0 1 1 1 1
DIF1 0 0 1 1 0 0 1 1
DIF0 0 1 0 1 0 1 0 1
AK4114DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S
AK4114SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I
default
Table 2. Setting for AK4114 Audio Interface Format OCKS1 0 1 MCKO1 256fs 512fs X'tal 256fs 512fs
default
Table 3. AK4114 Master Clock Setting
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Other jumper pins set up
Main Board [JP1] (GND): Analog ground and Digital ground OPEN: Separated. SHORT: Common. (The connector "DGND" can be open.) [JP3] (HVDD_SEL): HVDD of the AK4673 OPEN: HVDD is supplied from "HVDD" jack. SHORT: Supplied from the regulator ("HVDD" jack should be open). [JP4] (AVDD_SEL): AVDD of the AK4673 OPEN: AVDD is supplied from "AVDD" jack. SHORT: Supplied from the regulator ("AVDD" jack should be open). [JP5] (DVDD_SEL): DVDD of the AK4673 OPEN: DVDD is supplied from "DVDD" jack. SHORT: DVDD is supplied from "AVDD" ("DVDD" jack should be open). [JP6] (TVDD_SEL): TVDD of the AK4673 OPEN: TVDD is supplied from "TVDD" jack. SHORT: TVDD is supplied from "DVDD" ("TVDD" jack should be open). [JP7] (VCC_SEL): VCC of the AK4673 OPEN: VCC is supplied from "VCC" jack. SHORT: VCC is supplied from "TVDD" ("VCC" jack should be open). [JP16] (MKFS): MCLK Frequency 256fs: 256fs. 512fs: 512fs. 1024fs: 1024fs. 384/768fs: 384fs MCKO: MCKO is used. [JP17] (BCFS): BICK Frequency 32fs: 32fs (When MCLK is 256fs or 512fs or 768fs or 1024fs.) 64fs: 64fs (When MCLK is 256fs or 512fs or 768fs or 1024fs.) 32fs-384: 32fs (When MCLK is 384fs.) 64fs-384: 64fs (When MCLK is 384fs.) [JP22] (4114_MCKI): AK4114 Clock Source OPEN: X'tal of AK4114 is used. SHORT: X'tal of AK4114 is not used. [JP25] (CTRL_SEL):Serial Control Interface (Must be set to I2C) 3-WIRE: Invalid I2C: I2C-bus Control Mode
Sub Board [JP100] (I2CA_SEL): I2C (Must be set to H) H: Enable L: Unable
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The function of the toggle SW
[SW1] (PDN): Power down of AK4673. Keep "H" during normal operation. [SW2] (DIR): Power down of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4673 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4673.Table 3 shows switch and jumper settings for serial control.
Connect PC
10 wire flat cable
10pin Connector
CSN CCLK/SCI CDTI/SDA CDTO/ACK PENIRQN AKD4673 PORT4
Figure 9. Connect of 10 wire flat cable
Mode I2C CAD0=0 CAD0=1
S1 I2C ON ON CAD0 OFF ON
JP25 CTRL_SEL I2C
JP100 I2CA-SEL H
Table 4. Serial Control Setting
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Analog Input/Output Circuits
(1) Input Circuits (1-1) LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4 Input Circuit
JP112 LIN1 R110 2.2k
MPWR
JP113 RIN1
6
R111 2.2k LIN1 RIN1
J1 LIN1/RIN1
4 3
J2 LIN
2 3 4 5 1
C30 1u +
R10 (short)
JP8 LIN2 LIN3 LIN4 LIN_SEL
LIN2
LIN3
LIN4 J3 RIN
2 3 4 5 1
C31 1u +
R11 (short)
JP9 RIN2 RIN3 RIN4 RIN_SEL
RIN2
RIN3
RIN4
Figure 10. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4 Input Circuit LIN2/RIN2, LIN3/RIN3, LIN4/RIN4 shares J2/J3. JP8 (LIN_SEL) and JP9 (RIN_SEL) select each path. When microphone is connected to J1, JP112 and JP113 should be short. When LIN3/RIN3 paths of AK4673 are used, JP101 and JP108 should be set as below. AIN3bit ="1" (Register Address 21H)
M IN VCOC
LIN 3 JP 108 JP 101
R IN 3
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When MIN (shared with LIN3) Input path of AK4673 is used, JP108 should be set as below. AIN3bit ="0" (Register Address 21H)
MIN
LIN3 JP108
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(2) Output Circuits (2-1) HP Output Circuit
1
J7 HPL
RCA + HPL R17 (short) C35 220u JP12 HPL HP
R18 16
2 3 4 5
6
J9 HP/LINE
HP + HPR R19 (short) C36 220u JP13 HPR RCA R20 16
4 3
1
J8 HPR
2 3 4 5
Figure 11. HP Output Circuit (2-1-1) In case that signal is output from J7 and J8.
JP12 HPL JP13 HPR
RCA
HP
RCA
HP
(2-1-2) In case that signal is output from J9.
JP12 HPL JP13 HPR
RCA
HP
RCA
HP
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(2-2)
LOUT/ROUT (LOP/LON) Output Circuit
6
J9 HP/LINE
3.5ST + LOUT C33 1u JP10 LOUT_SEL RCA R13 220 R14 10k
4 3
1
J5 LOUT
2 3 4 5
3.5ST + ROUT C34 1u JP11 ROUT_SEL RCA R15 220 R16 10k J6 ROUT
2 3 4 5
1
Figure 12. LOUT/ROUT(LOP/LON) Output Circuit (2-1-1) In case that signal is output from J5 and J6.
JP10 LOUT_SEL JP11 ROUT_SEL
RCA
3.5ST
RCA 3.5ST
(2-1-1) In case that signal is output from J9.
JP10 LOUT_SEL JP11 ROUT_SEL
RCA
3.5ST
RCA 3.5ST
AKM assumes no responsibility for the trouble when using the above circuit examples.
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Control Software Manual For the Evaluation of CODEC Set-up of evaluation board and control software
1. Set up the AKD4673-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4673-A by 10-line type flat cable (packed with AKD4673-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK4673-A Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4673.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button.
Explanation of each buttons
[Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : [Filter] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4673. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Set Programmable Filter (FIL1, FIL3, EQ) of AK4673 easily.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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2007/5
[AKD4673-A]
Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4673, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4673, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL
Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4673 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4673, click [OK] button. If not, click [Cancel] button.
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2007/5
[AKD4673-A]
4. [Save] and [Open] 4-1. [Save]
Save the current register setting data. The extension of file name is "akr".
(Operation flow)
(1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is "akr". 4-2. [Open] The register setting data saved by [Save] is written to AK4673. The file type is the same as [Save].
(Operation flow)
(1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.
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2007/5
[AKD4673-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is "aks".
Figure 13. Window of [F3]
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2007/5
[AKD4673-A]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure 14 opens.
Figure 14. [F4] window
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2007/5
[AKD4673-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 15.
Figure 15. [F4] window(2) (2) Click [START] button, then the sequence is executed.
3-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
3-3. Note
(1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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2007/5
[AKD4673-A]
7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 16 opens.
Figure 16. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 17. (2) Click [WRITE] button, then the register setting is executed.
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2007/5
[AKD4673-A]
Figure 17. [F5] windows (2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.
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[AKD4673-A]
8. [Filter Dialog] This dialog can easily set the AK4673's programmable filter.
Figure 18. [Filter] window
8-1. Value input columns on left side
[Sampling Rate] [Cut Off Frequency of FIL1] [Cut Off Frequency of FIL3] [Pole Frequency of EQ] [Zero Frequency of EQ] [FIL3 GAIN] [EQ GAIN] Input value of sampling frequency [unit : Hz] Input value of cut off frequency of FIL1 [unit : Hz] Input value of cut off frequency of FIL3 [unit : Hz] Input value of pole frequency of EQ [unit : Hz] Input value of zero frequency of EQ [unit : Hz] Input value of gain of FIL3 (0~-10dB) [unit : dB] Input value of gain of EQ (+12~0dB) [unit : dB]
8-2. Check box on left side
Check Box FIL1 FIL3 EQ LPF of FIL1 LPF of FIL3 Check FIL1 bit ="1" FIL3 bit ="1" EQ bit ="1" F1AS bit ="1"(LPF) F3AS bit ="1"(LPF) Check off FIL1 bit ="0" FIL3 bit ="0" EQ bit ="0" F1AS bit ="0"(HPF) F3AS bit ="0"(HPF)
8-2. [Register Setting] panel and [Register Setting] button on right side
Click [Register setting] button, then filter coefficient set by 8-1 and 8-2 is written on [Register setting] panel. (It is also written to the actual control register of the AK4673.)
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2007/5
[AKD4673-A]
Control Software Manual For the Evaluation of TSC
Parallel Port Driver install Attached software is the application software, which checks the function of the AK4673. Windows(R) Win 98, Win 2K, and Win XP are supported. However, to make it operate on Win2K and XP, it is necessary to install driver in advance. Please follow a procedure with reference to DriverSetupe.pdf. Installation of a driver is unnecessary to use it by the Windows 98 system. Run the software (AK4673_TSC.exe) This software valuates the function of the AK4673 TSC block. First match Port Address of your PC environment. Measurements with pressed by pen or stylus on the touch panel are started when the start button is clicked after select Channel Selection, MODE, and Power Down 0. A result will be displayed on AD OUT Section. When carrying out position detection, the position where pen clicked on the touch panel is measured. Operation can set up two control commands. Continuous operation can be performed. Each data (mean, max, and min) is also displayed at the same time. PENIRQN can be seen by the break of a command.
Figure 19. TSC control soft window
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2007/5
[AKD4673-A]
Trouble Shooting 1. Application error is occurred and doesn't start up If the operating system is Window2000/XP, Please install AKM port driver in advance of run the AK4673_TSC.exe. 2. MEAN value in AD OUT section does not change until click start button (cannot write control command to AK4673). Please set the port address correctly to your PC platform environment. 3. The mean, max, min value doesn't change wherever the pen is pressed down on the panel. There is a possibility of the trouble of the contact of the relay connector (plat 8pin-8-wire female dip converter) that connects the touch panel. Measure panel seat resistance (XP-XN, YP-YN), and check the resistance. Generally, the panel seat resistance is hundreds of . There is a possibility that the touch panel is not correctly connected if the resistance is over thousands of k. Please connect the connector and check the resistance value again.
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2007/5
[AKD4673-A]
Revision History
Date (YY/MM/DD) 07/05/30 Manual Revision KM086000 Board Revision 0 Reason First edition Contents
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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2007/5
A
B
C
D
E
CSN/CAD0
12
11
10
9
8
7
6
5
4
3
2
L
3
H
1
14
E
C20 0.1u
7
Vcc GND
C19 0.1u
XN XP TP137 PDN
1
1
1
1
74HC14
SW1 PDN
R109 51
TP130 TP131 VSS1 AVDD
MPWR TP129
1
1 2 3 4 5 6
1A 1Y 2A 2Y 3A 3Y
4Y 4A 5Y 5A 6Y 6A
8 9 10 11 12 13
R8 10k
K
U2
D1 HSU119
TouchScreen
8 7 6 5 4 3 2 1
A
YN YP
CN2 12pin
I2C
VCC
AVDD
R106 2.2k R107 2.2k
JP110 JP111
RIN1 LIN1
E
2
J100
C117 4.7n XN YN YP R108 10k JP101 VCOC-SEL VCOC C120 0.01u TP135 VCOC/RIN3
1
TP133 I2CA
1
XP
TP138 YN
1
TP136 XN
1
1
1
RIN3
TP132 TP134 XP YP C115 10u C116 0.1u
C2 C1 B1 A1
AVDD-IN
JP100 H AVDD-IN L I2CA-SEL
1
TP139 CADA
H1 J1
C121 0.01u
C119 0.01u
C118 0.01u
G1
G2
U1
YP
YN
XN
VCOC
NC
NC
XP
CADA
PDN
MPWR
AVDD
VSS1
I2CA
NC
CN4 JP102
13
D
F2
E2
D2
D1
E1
F1
+
SDAA SDAT SCLA SCLT
1
J2
SDAA
VCOM
A2
JP103 JP104 JP105
TP101 SCLA
H2 SCLA RIN1/IN1+ B2
14
H3 15
SDTI
LIN1/IN1-
A3
R100
16
J3
SDTO
NC
B3
+
CCLK/SCL
17
CDTI/SDA
18
TP102 SDTI R101
1
J4
BICK
LIN2/IN2-
B4
4371_SDTI
19
TP103 51 SDTO R102
1
TP123 RIN2
43
1
1
TSVDD
1
H4
LRCK
TSVDD
A4
C109 0.1u
1
+
H5
1 VSS3
4371_SDTO
20
51 TP104 LRCK R103
1
TP107
J5
NC
VSS3
4371_LRCK
21
TP105 51 BICK R104
1
J6
1 TVDD2
4371_BICK
C
51 1 TP106 DVDD
TP108
DVDD
MIN/LIN3
B6
TP120 ROUT
40
1
1
AK4673
RIN2
B5
NC
A5
C100+ 10u C102+ 10u
1 TVDD1
C101 0.1u
H6 TVDD2 LOUT/LOP A6
22
JP106 TVDD2
DVDD
23
C103 0.1u
H7 NC ROUT/LON A7
R105 open
TVDD
24
JP107 TVDD1
TP109
J7
TVDD1
LIN4/IN4+
B7
PENIRQN-OUT 12pin
C104+ 10u
C105 0.1u
H8 MCKO NC B8
J9
PENIRQN
NC MCKI
RIN4/IN4MUTET HVDD CADT SDAT VSS2 SCLT HPR HPL
A8
NC
NC
G8
G9
F8
F9
E8
E9
B9
D8
D9
C8
1
1
1
TP140 TP141 TP142 CADT SDAT SCLT
B
+
10u C107
C108 1u
B
1
TP116 PENIRQN
1
1
25
26
27
28
29
30
31
32
33
34
35
A
36
CN3 12pin
1
TP110 MCKI
TP111 MCKO
1TP113 TP112 HVDD TP114 TP115 VSS2 HPR HPL
1
1
1
TP118 RIN4
1
C106 0.1u +
C9
H9
TP117 MUTET
A9
J8
NC
NC
4371_MCKO
4371_MCKI
HVDD
RIN4
SPN
HPR
SPP
HPL
A
B
C
+ +
51
+ +
1
TP100 SDAA
C113 0.1u
CN1 C114 2.2u TP128 VCOM
1
1
TP127 RIN1
RIN3
48
D
LIN3
47
C112 1u
46
RIN1
C110 10u
TP125 TSVDD JP109
TP126 LIN1
C111 1u
45
LIN1 TP124 LIN2
44
LIN2
RIN2 R12 20k LOUT
41
LIN3 JP108 MIN-SEL MIN
42
TP122 LIN3/MIN 1
TP121 LOUT
ROUT
C
39
LIN4
38
TP119 1 LIN4
37
12pin
A
Title Size Document Number
AKD4673-A
Rev
A2
Date:
D E
AK4673
Monday, December 11, 2006
Sheet
0 1
of
5
A
B
C
D
E
+
T1 TA48033F
1
E
3.5ST LOUT JP10 LOUT_SEL RCA R13 220
1
IN C21 0.1u
GND
REG1
1
OUT C22 + 0.1u
T45_RED
C23 47u
C33 1u
J5 LOUT
2 3 4 5
E
AGND1
R14 10k
1
T45_BK L1 (short)
1 1 2 1
2
+
HVDD1
JP3 HVDD_SEL HVDD
6
J1 LIN1/RIN1
LIN1 RIN1 ROUT C34 1u
3.5ST JP11 ROUT_SEL RCA R15 220
1
4 3
T45_OR
+
2
C24 47u
J6 ROUT
2 3 4 5
R16 10k JP4 AVDD_SEL
2
D
AVDD1
L2
1 1 1
AVDD
2 3 4 5
T45_OR
+
2
C25 47u
(short)
J2 LIN
1
C30 1u +
R10 (short)
JP8 LIN2 LIN3 LIN4 LIN_SEL
LIN2
D
LIN3
R9 10 JP5 DVDD_SEL
LIN4
1
J7 HPL RCA R18 16
2 3 4 5
+
DVDD1
L3
1 1 1 2
DVDD
T45_OR
+
2
C26 47u
(short)
HPL R17 (short) C35 220u
JP12 HPL HP
JP6 TVDD_SEL J3 RIN
C
TVDD1
L4
1 1 1 2
C31 1u
1
R11 (short)
JP9 RIN2 RIN3 RIN4 RIN_SEL
RIN2
6 4 3
J9 HP/LINE
C
TVDD
T45_OR
+
2
C27 47u
(short)
2 3 4 5
RIN3
+
+
RIN4 HP JP7 VCC_SEL HPR R19 (short) C36 220u JP13 HPR RCA R20 16
2 1
JP1 GND VCC1 L5
1 1 1
J8 HPR
2 3 4 5
VCC
T45_OR
+
2
C28 47u
(short)
B
D3V1
1 1
1
2
+
L6 D3V SPP T45_OR +
2
C37 1u
6
B
J10 SPK/MOUT R22 10k
4 3
C29 47u
(short) R21 (open) SPN C38 (short) +
DGND1
1
T45_BK
R23 (open)
JP26 MOUT
A
A
Title Size Document Number
AKD4673-A
Power Supply, I/O
Sheet
E
Rev
A3
Date:
A B C D
0
of
Monday, December 11, 2006
2
5
A
B
C
D
E
E
E
D3V
EXT_MCLK
4114_BICK
D
EXT_BICK JP18 BICK_SEL
JP16 4114_MCKO JP15 MCLK
1 2 3 4 5 6 14 13 12 11 10 9 8
J11 EXT
2 3 4 5 1
DIR R24 51 JP14 EXT EXT
1CLR 2CLR 1D 2D 1CK 2CK 1PR 2PR 1Q 2Q 1Q 2Q Vcc GND
256fs 512fs 1024fs 384/768fs MCKO MKFS
JP17
10 11 CLK Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VD Q9 Q10 Q11 DGND Q12 RST 9 7 6 5 3 2 4 13 12 14 15 1
DIR 4040
EXT_LRCK THR JP19 INV PHASE
D
64fs-384 32fs-384 64fs 32fs fs-384 fs JP20 LRCK BCFS
4040 DIR JP21 LRCK_SEL
A K 1 2 3 4 5 6 14 1A 1Y 2A 2Y 3A 3Y Vcc GND 3 4Y 4A 5Y 5A 6Y 6A 8 9 10 11 12 13
16
C39 0.1u
7
C42 0.1u
8
LED1 ERF
U3 74AC74
3 4 5 6 10 7 2 9 1 A B C D QA QB QC QD Carry 14 13 12 11 15
U6 74HC4040 4114_LRCK
R26 1k 4114_INT0 4114_PDN
ENT ENP Vcc CLK LOAD CLR GND
16
7
8
U4
74AC163
C44 0.1u
L
1
C40 0.1u
C43 0.1u
U7 74HC14
A
MCKO
R25 10k
K
C
D2 HSU119
C
H SW2 DIR
8 9 10 11 12 13
U5 74HCU04
GND Vcc
B
B
1 2 3 4 5 6
1A 1Y 2A 2Y 3A 3Y
4Y 4A 5Y 5A 6Y 6A
14
7
C41 0.1u
A
2
A
Title Size Document Number
AKD4673-A
CLOCK
Sheet
E
Rev
A3
Date:
A B C D
0 3
of
Monday, December 11, 2006
5
A
B
C
D
E
D3V
E
PORT1
VCC GND OUT 3 2 1
L7 (short)
1 2
E
C45 0.1u
C46 0.1u
TORX141
R27 470
C54 10u + C55 C56 0.47u
41 48 46 45 44 42 39 47 43 40
0.1u R28 18k
38 37 INT1
VCC U8
12 11 10 9 8 7
D
AVSS
TEST1
VCOM
RX3
RX2
RX1
RX0
NC
NC
R
AVDD
H L
123456
D
------OFF------
S1 SW DIP-6
1
IPS0
INT0
36
4114_INT0
DIF2 DIF1 DIF0 OCKS1 CAD0 I2C
1 2 3 4 5 6
2
NC
OCKS0
35
3
DIF0
OCKS1
34
CAD0 I2C
7 6 5 4 3 2 1
4
TEST2
CM1
33
5
DIF1
CM0
32
C
6
NC
PDN
31
RP1 47k
7 DIF2
AK4114
XTI IPS1 XTO
4114_PDN C53 5p
1
C
MCKO JP22 4114_MCKI X1 11.2896MHz
30
9
P/SN
DAUX
28
2
8
29
C52 5p DAUX
10
XTL0
MCKO2
27
11
XTL1
BICK
26
4114_BICK
B
B
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK TX0 TX1
SDTO
25
4114_SDTO
C49 0.1u +
C51 0.1u +
13
14
15
16
17
18
19
20
21
22
23
24
4114_LRCK C48 10u C50 10u
PORT2
IN VCC
A
4114_MCKO
3 2
C47 0.1u
1
A
GND
TOTX141
Title Size Document Number
AKD4673-A
DIR/DIT
Sheet
E
Rev
A3
Date:
A B C D
0 4
of
Monday, December 11, 2006
5
A
B
C
D
E
VCC D3V
3 4 5 6 7
U9
A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18 17 16 15 14 7 6 5 4 3 2 1
EXT_BICK
E
4371_BICK 4371_LRCK
E
EXT_LRCK
R29 10k PORT3 MCLK BICK LRCK SDTI VCC
1 3 5 7 9 2 GND 4 GND 6 8 10 SDTO
7 6 5 4 3 2 1
8 9 10
RP2 47k
2 1 DIR VCCA GND GND GND 13 OE VCCB VCCB 22 24 23
RP3 47k
Slave
DSP
D
C57 0.1u
11 12
C58 0.1u
3 4
U10
D
Master
JP23 M/S
A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
21 20 19 18 17 16 15 14
4371_MCKO
74AVC8T245
5 6 7
MCKO PENIRQN DAUX
8 9 10
PENIRQN-OUT
4371_SDTO
2 1
C
DIR VCCA GND GND
OE VCCB VCCB GND
22 24
C
JP24 ADC SDTI_SEL 4114_SDTO EXT_MCLK DIR
3 4 5
C59 0.1u
11
23
U11
A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18 17 16 15 14
C60 0.1u
13
12
74AVC8T245
4371_MCKI 4371_SDTI CSN/CAD0 CCLK/SCL CDTI/SDA
B
CAD0 I2C PORT4
10 8 6 4 2 9 7 5 3 1
6
R30 10k
R31 10k
R32 10k R33 R34 R35 470 470 470
JP25 CTRL_SEL
7 8
3-WIRE
9 10
B
CSN CCLK/SCI CDTI/SDA CDTO/SDA(ACK) PENIRQN
2
CTRL
1
DIR VCCA GND GND
OE VCCB VCCB GND
22 24 23
PENIRQN
C61 0.1u
11 12
C62 0.1u
13
74AVC8T245
U12
1 3 5 9 11 13 14 1A 2A 3A 4A 5A 6A Vcc
Size Document Number
A
1Y 2Y 3Y 4Y 5Y 6Y
2 4 6 8 10 12
R36 1k
A
Title
C63 0.1u
7
AKD4673-A
LOGIC
Sheet
E
Rev
GND
A3
Date:
C D
0 5
of
74LVC07
A B
Tuesday, October 17, 2006
5

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